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HTMOSTM High Temperature Products
HIGH TEMPERATURE 32K x 8 STATIC RAM
FEATURES
* Specified Over -55 to +225C * Fabricated with HTMOSTM IV Silicon on Insulator (SOI) * Read/Write Cycle Times 50 ns Support 20 MHz Clock * Asynchronous Operation * CMOS Input/Output Buffers * Single 5 V 10% Power Supply * Hermetic 28-Lead Ceramic DIP
HT6256
APPLICATONS
* Down-Hole Oil Well * Avionics * Turbine Engine Control * Industrial Process Control * Nuclear Reactor * Electric Power Conversion * Heavy Duty Internal Combustion Engines
GENERAL DESCRIPTION
The 32K x 8 High Temperature Static RAM is a high performance 32,768 word x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell's HTMOSTM technology, and is designed for use in systems operating in severe high temperature environments. The RAM requires only a single 5 V 10% power supply and has CMOS compatible I/O. Power consumption is typically less than 30 mW/MHz in operation, and less than 10 mW when de-selected. The RAM read operation is fully asynchronous, with an associated typical access time of 50 ns at 5 V. The RAM provides guaranteed performance over the full -55 to +225C temperature range. Typically, parts will operate up to +300C for a year, with derated performance. All parts are burned in at 250C to eliminate infant mortality.
PACKAGE PINOUT
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Top View
VDD NWE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3
Solid State Electronics Center * 12001 State Highway 55, Plymouth, MN 55441 * (800) 323-8295 * http://www.ssec.honeywell.com
HT6256
FUNCTIONAL DIAGRAM
A:0-8,12-13 Row Decoder
* * *
11
32,768 x 8 Memory Array
* * *
CE* NCS
Column Decoder Data Input/Output NWE
WE * CS * CE
8 8 DQ:0-7
NOE
NWE * CS * CE * OE (0 = high Z)
Signal
1 = enabled # Signal
A:9-11, 14
4
All controls must be enabled for a signal to pass. (#: number of buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14 DQ: 0-7 NCS Address input pins which select a particular eight-bit word within the memory array. Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers. If this signal is not used it must be connected to VSS. Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level NWE allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS and NWE. If this signal is not used it must be connected to VSS. External control of Chip Enable is an extra feature available only in other package options. Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input buffer. If this signal is not used it must be connected to VDD.
NWE NOE
CE*
TRUTH TABLE
NCS L L H X CE* H H X L NWE H L XX XX NOE L X XX XX MODE Read Write Deselected Disabled DQ Data Out Data In High Z High Z
Notes: X: VI=VIH or VIL XX: VSSVIVDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X
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HT6256
ABSOLUTE MAXIMUM RATINGS (1)
Rating Symbol VDD VPIN TSTORE TSOLDER PD IOUT VPROT Parameter Supply Voltage Range (2) Voltage on Any Pin (2) Storage Temperature (Zero Bias) Soldering Temperature (5 Seconds) Maximum Power Dissipation (3) DC or Average Output Current ESD Input Protection Voltage (4) Thermal Resistance (Jct-to-Case) 28 DIP 2000 10 Min -0.5 -0.5 -65 Max 6.5 VDD+0.5 325 355 2 25 Units V V C C W mA V C/W
JC
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description Symbol VDD TA VPIN Parameter Supply Voltage (referenced to VSS) Ambient Temperature Voltage on Any Pin (referenced to VSS) Min 4.5 -55 -0.3 Typ 5.0 25 Max 5.5 225 VDD+0.3 Units V C V
CAPACITANCE (1)
Symbol CI CO Parameter Input Capacitance Output Capacitance Typical (2) 5 7 Worst Case Min Max 7 9 Units pF pF Test Conditions
VI=VDD or VSS, f=1 MHz VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only (2) Typical operating conditions: TA= 25C.
DATA RETENTION CHARACTERISTICS (1)
Symbol VDR IDR Parameter Data Retention Voltage Data Retention Current Typical Worst Case Min 2.5
500 330
Max
Units V
A A
Test Conditions
NCS=VDR VI=VDR or VSS NCS=VDD=2.5V, VI=VDD or VSS NCS=VDD=3.0V, VI=VDD or VSS
(1) Operating conditions: TA= -55C to +125C.
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HT6256
DC ELECTRICAL CHARACTERISTICS
Worst Case (2) Symbol IDDSB1 Parameter Static Supply Current Test Conditions VIH=VDD, IO=0 VIL=VSS, f=0MHz NCS=VDD, IO=0, f=40 MHz f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (3) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (3) VSS VI VDD Typ (1) 0.2 0.2 3.4 2.8 -5 -10 1.7 3.2 0.3 0.005 4.3 4.5 4.2 Vdd-0.05 0.7xVdd 0.4 0.05 Min Max 2.0 2.0 4.0 4.0 +5 +10 0.3xVdd Units mA mA mA mA A A V V V V V V
IDDSBMF Standby Supply Current--Deselected IDDOPW IDDOPR II IOZ V IL VIH VOL VOH Dynamic Supply Current--Selected (Write) Dynamic Supply Current--Selected (Read) Input Leakage Current Output Leakage Current Low-Level Input voltage high-Level Input Voltage Low-Level Output voltage High-Level Output Voltage
VSS VIO VDD Output=high Z March Pattern March Pattern VD =4.5V, IOL=10 mA (CMOS) VDD=4.5V, IO =200 A VDD=4.5V, IOH=-5 mA VDD=4.5V, IOH=-200 A
(1) Typical operating conditions: VDD= 5.0 V,TA=25C. (2) Worst case operating conditions: VDD= 5.0 V 10%, TA=-55C to +225C. (3) All inputs switching. DC average current. External control of Chip Enable (CE) is available only in other package options.
2.9 V Vref1 249 DUT output Vref2
+ -
Valid high output
+ -
Valid low output
CL >50 pF* *CL = 5 pF for TWLQZ, TSHQZ, and TGHQZ
Tester Equivalent Load Circuit
Operating Current vs. Frequency @ 225C
70
Cycle Times vs. Temperature
30
Write
60
Read
Operating Current (mA)
50
40
Cycle Time (ns)
Read
25
30
Write
20
20
10
0 0 5 10 15 20 25 Frequency (MHz)
15 -100
0
100 Temperature (C)
200
300
4
HT6256
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3) Symbol TAVAVR TAVQV TAXQX TSLQV TSLQX TSHQZ TGLQV TGLQX TGHQZ TEHQV TEHQX TELQZ Parameter Address Read Cycle Time Address Access Time Address Change to Output Invalid Time Chip Select Access Time Chip Select Output Enable Time Chip Select Output Disable Time Output Enable Access Time Output Enable Output Enable Time Output Enable Output Disable Time Chip Enable Output Access Time (4) Chip Enable Output enable Time (4) Chip Enable Output Disable Time (4) 17 10 4 5 10 0 15 25 5 20 15 3 50 Typical (2) Min 50 50 Max ns ns ns ns ns ns ns ns ns ns ns ns Units
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ and TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VDD=5.0 V, TA=25C. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 225C. (4) External control of Chip Enable (CE) is available only in other package options.
TAVAVR
ADDRESS
TAVQV TSLQV TAXQX
NCS
TSLQX TSHQZ DATA VALID
DATA OUT
HIGH IMPEDANCE TEHQX TEHQV
TELQZ
CE
TGLQX TGLQV TGHQZ
NOE
(NWE = high)
5
HT6256
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3) Symbol TAVAVW TWLWH TSLWH TDVWH TAVWH TWHDX TAVWL TWHAX TWLQZ TWHQX TWHWL TEHWH Parameters Write Cycle Timing (4) Write Enable Write Pulse Width Chip Select to End of Write Time Data Valid to End of Write Time Address Valid to End of Write Time Data Hold Time after End of Write Time Address Valid Setup to Start of Write Time Address Valid after End of Write Time Write Enable to Output Disable Time Write Disable to Ouput Enable Time Write Disable to Write Enable Pulse Width (5) Chip Enable to End of Write Time (6) Typical (2) Min 50 45 45 35 45 0 0 0 0 5 5 45 15 Max ns ns ns ns ns ns ns ns ns ns ns ns Units
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ. (2) Typical operating conditions: VDD=5.0 V, TA=25C. (3) Worst case operation conditions: VDD=4.5 V to 5.5 V, -55 to 225C. (4) TAVAVW = TWLWH + TWHWL (5) Guaranteed but not tested. (6) External control of Chip Enable (CE) is available only in other package options.
TAVAVW
ADDRESS
TAVWH TAVWL TWHWL TWLWH TWHAX
NWE
TWLQZ TWHQX
DATA OUT
HIGH IMPEDANCE
TDVWH DATA VALID TSLWH
TWHDX
DATA IN
NCS
TEHWH
CE
6
HT6256
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high, and toggling the addresses. For an address activated read cycle, NCS and CE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS, however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. To control a read cycle with CE, all addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TELQZ time following a disabling CE edge transition. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by write enable (NWE), chip select (NCS), or chip enable (CE) edge transitions (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low, and CE must be high. Consecutive write cycles can be performed with NWE or NCS held continuously low, or CE held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. The write mode can be controlled via three different control signals: NWE, NCS, and CE. All three modes of control are similar except the NCS and CE controlled modes actually disable the RAM during the write recovery pulse. Both CE and NCS fully disable the RAM decode logic and input buffers for power savings. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity. However, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/TAVSH/ TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/ TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV.
7
HT6256
QUALITY ASSURANCE Honeywell maintains a high level of product integrity through process control utilizing statistical process control, a complete "Total Quality Assurance System," and a computer data base process performance tracking system. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening. SCREENING LEVELS Honeywell offers several levels of device screening to meet your system needs. Hi-Rel Level B devices undergo additional screening per the requirements of MIL-STD-883. RELIABILITY Honeywell understands the stringent reliability requirements for extreme environment systems and has extensive experience in reliability testing on programs of this nature. Reliability attributes of the HTMOS process were characterized by testing test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure reliable -55 to +225C specified products. PACKAGING The standard package is a hermetic 28-lead DIP constructed of multilayer ceramic (Al2O3) and features internal power and ground planes. Ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. These capacitors connect to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package. For packaging options with surface mount capability or external control of Chip Enable (CE), call Honeywell.
28-LEAD DIP PACKAGE
D Z Y C
All dimensions in inches
Right Reading on Lid
E eA A b b2 C D E e eA L Q S1 S2 X Y Z 0.175 (max) 0.018 0.002 0.050 (typ) 0.010 to 0.002 1.400 0.014 0.594 0.010 0.100 0.005 0.600 0.010 0.125 to 0.175 0.050 0.010 0.005 (min) 0.005 (min) 0.100 ref 0.050 ref 0.075 ref
Ceramic Body
1
X
Optional Capacitors S2
A L
Q
b2
S1 b (width) e (pitch)
ORDERING INFORMATION (1)
HT6256DC D - Indicates package type D = 28-Lead DIP For packaging options, call Honeywell
(1) Orders may be faxed to 612-954-2257. Please contact our Customer Service Department at 612-954-2888 for further information.
C - Indicates screening level B = High Temperature Class B C = Commercial
To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
900202 Rev. B 4-98
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